1. Field of the Invention
The present invention relates to an organic electroluminescent display device and method of fabricating the same, and more particularly, to a dual panel type organic electroluminescent display device and a method of fabricating the same.
2. Discussion of the Related Art
Among flat panel display devices, since an organic electroluminescent display device is self-luminescent and does not require an additional light source, the organic electroluminescent display device has a wide viewing angle, high contrast ratio, and a small size and is light weight, as compared to a liquid crystal display device. The organic electroluminescent display device also has a low power consumption. In addition, the organic electroluminescent display device is driven by a low direct current voltage and a short response time. Because all elements of the organic electroluminescent display device are solid, the organic electroluminescent display device can be used in a wide range of temperatures and is unlikely to be damaged by external impacts. Furthermore, the organic electroluminescent display device can have reduced manufacturing costs. Especially, the organic electroluminescent display device has simple manufacturing processes as compared with the liquid crystal display device or a plasma display panel, and only deposition and encapsulation apparatuses are used for manufacturing the organic electroluminescent display device.
FIG. 1 is a cross-sectional view of an organic electroluminescent display device according to the related art. In FIG. 1, the organic electroluminescent display device includes a first substrate 10 and a second substrate 60 facing the first substrate with a predetermined space therebetween. An array element layer AL is formed on an inner surface of the first substrate 10. The array element layer AL includes a thin film transistor T formed at each pixel region P, which is a minimum unit for an image. An organic electroluminescent diode E is formed on the array element layer AL. The organic electroluminescent diode E includes a first electrode 48, an organic light-emitting layer 54 and a second electrode 56 sequentially formed. Light emitted from the organic light-emitting layer 54 is transmitted toward a transparent electrode of the first and second electrodes 48 and 56. The organic electroluminescent display device is categorized into a top emission mode and a bottom emission mode depending on an emission direction. Here, the organic electroluminescent display device has the bottom emission mode, where the first electrode 48 is formed of a transparent material and the light emitted from the organic light-emitting layer 54 is transmitted through the first electrode 48.
The second substrate 60 serves as a sort of an encapsulation substrate. A concavity 62 is formed at an inner surface of the second substrate 60 and a desiccant 64 is disposed within the concavity 62. The desiccant 64 removes any external moisture that may permeate into a space between the first and second substrates 10 and 60 and protects the organic electroluminescent diode E. A seal pattern 70 is formed along peripheral portions of the first and second substrates 10 and 60 and seals the first and second substrates 10 and 60.
FIG. 2A is a plan view of a pixel for an organic electroluminescent display (OELD) device of the related art and FIG. 2B is a cross-sectional view along the line II-II of FIG. 2B. In FIGS. 2A and 2B, a buffer layer 12 is formed on a substrate 10, and a semiconductor layer 14 and a capacitor electrode 16 are formed on the buffer layer 10 with a space therebetween. A gate insulating layer 18 and a gate electrode 20 are sequentially formed on a center portion of the semiconductor layer 14. The semiconductor layer 14 includes an active area 14a corresponding to the gate electrode 20 and source and drain areas 14b and 14c disposed at both sides of the active area 14a. A gate line 22 in a first direction is also formed on the same layer as the gate electrode 20.
A first passivation layer 24 covers the gate electrode 20 and the capacitor electrode 16. A power electrode 26 is formed over the first passivation layer 24 corresponding to the capacitor electrode 16, and the power electrode 26 extends from a power supply line 28, which is formed in a second direction crossing the first direction.
A second passivation layer 30 is formed on an entire surface of the substrate 10 including the power electrode 26. The first and second passivation layers 24 and 30 include first and second contact holes 32 and 34 therethrough. The first contact hole 32 exposes the drain area 14c of the semiconductor layer 14 and the second contact hole 34 exposes the source area 14b of the semiconductor layer 14. The second passivation layer 30 also has a third contact hole 36 exposing a part of the power electrode 26.
A source electrode 38 and a drain electrode 40 are formed on the second passivation layer 30. The drain electrode 40 is connected to the drain area 14c of the semiconductor layer 14 through the first contact hole 32. The source electrode 38 is connected to the source area 14b of the semiconductor layer 14 through the second contact hole 34 and the power electrode 26 through the third contact hole 36.
As shown in FIG. 2A, a data line 42 is formed on the same layer as the source and drain electrodes 38 and 40 in the second direction. The data line 42 crosses the gate line 22 to define a pixel region P. A third passivation layer 44 covers the drain electrode 40 and the source electrode 38. The third passivation layer 44 has a drain contact hole 46 exposing a part of the drain electrode 40.
A light-emitting area EA is defined on the third passivation layer 44, and a first electrode 48 is formed in the light-emitting area EA. The first electrode 48 is connected to the drain electrode 40 through the drain contact hole 46. An inter insulating layer 50 is formed on the first electrode 48 and the third passivation layer 44. The inter insulating layer 50 exposes the main portion of the first electrode 48 and covers edges of the first electrode 48. An organic light-emitting layer 54 is formed on the first electrode 48 and the inter insulating layer 50 in the light-emitting area EA. A second electrode 56 is formed on an entire surface of the substrate 10 including the organic light-emitting layer 54.
The semiconductor layer 14, the gate electrode 20, the source electrode 38 and the drain electrode 40 constitute a thin film transistor. The thin film transistor of FIG. 2B is a driving thin film transistor Td. The driving thin film transistor Td is disposed between a switching thin film transistor Ts and the power supply line 28. The switching thin film transistor Ts is located at a crossing portion of the gate line 22 and the data line 42, and has the same structure as the driving thin film transistor Td.
Here, the gate electrode 20 of the driving thin film transistor Td is connected to the switching thin film transistor Ts and the drain electrode 40 of the driving thin film transistor Td is formed in an island shape. The switching thin film transistor Ts includes another gate electrode extending from the gate line 22 and another source electrode extending from the data line 42.
The power supply line 28 (including the power electrode 26) and the capacitor electrode 16 overlap each other to form a storage capacitor Cst.
The bottom emission mode OELD device is manufactured by attaching a substrate including array elements and organic luminescent diodes and another substrate for encapsulation. Since the yield of the OELD device depends on the yields of the array elements and the organic luminescent diodes, in the OELD device having the above structure, the whole processing yield is largely affected by the later organic luminescent diode process. Thus, even if the array elements are properly manufactured, if the organic light-emitting layer to be formed to a thickness of about 1,000 Å is improperly manufactured due to impurities or other factors, the resulting OELD device will be rejected as bad. In this case, all manufacturing costs and source materials required for the array elements are wasted, and the product yield is lowered.
Although the bottom emission mode OELD device has an excellent stability and a certain degree of freedom in its manufacturing processes, the bottom emission mode OELD device has a reduced aperture ratio. Thus, the bottom emission mode OELD device is not generally suitable for a high aperture device.
On the other hand, a top emission mode OELD device has a high aperture ratio, and is easy to manufacture. Additionally, the top emission mode OELD device has a long lifetime. However, in the top emission mode OELD device, since a cathode electrode is generally disposed over the organic light-emitting layer, a choice of material with which to make the cathode electrode is limited. Accordingly, the transmittance of light is limited, and a light-emitting efficacy is reduced. Furthermore, in order to improve the light transmittance, the passivation layer should be formed as a thin film, whereby the exterior moisture and air are not fully blocked.